1. Field of the Invention
The disclosed technology generally relates to electrostatic discharge protection devices that protect circuits from transient electrical events and more particularly to low-voltage triggered silicon-controlled rectifier devices implemented using a bulk fin field-effect transistor technology.
2. Description of the Related Technology
Certain electronic systems can be exposed to transient electrical events that last a relatively short duration and have rapidly changing voltages and/or currents. Transient electrical events can include, for example, electrostatic discharge (ESD) events arising from the abrupt release of charge from an object or a person to an electronic system. Such transient electrical events can potentially lead to core circuits being damaged, resulting in gate oxide punch-through, junction damage, metal damage, and surface charge accumulation, among others. Moreover, transient electrical events can induce latch-up (in other words, inadvertent creation of a low-impedance path), thereby disrupting the functions of and potentially causing permanent damage to the IC.
To protect the ICs inside electronic systems, some electronic systems incorporate electrostatic discharge (ESD) protection devices for protecting various structures and circuits during manufacturing and/or during operation of the electronic systems. ESD protection devices can be designed to be triggered, that is, switched from an ‘off’ state to an ‘on’ state, when they are exposed to an ESD event, such as an abnormal external electrical pulse. Under normal operation, these protection devices are normally returned to their normal ‘off’ state when the abnormal external pulse has subsided, and should be kept in an ‘off’ or non-operational state during normal operation of the semiconductor device and its associated circuit.
Some silicon-controlled rectifier (SCR) devices provide protection against electrostatic discharge due their superior area efficiency which provides electrostatic discharge robustness. However, some SCR devices have relatively high trigger voltages. Moreover, some SCR device suffer from the risk of mis-triggering into an ‘on’ state, followed by a transition into a latch-up state with high leakage currents, even under normal circuit operating conditions. The relatively high trigger voltages and the risk of latch-up can be prohibitive in certain applications, such as advanced complementary metal oxide semiconductor (CMOS) and power-rail electrostatic discharge protection technologies.
Low-voltage triggered silicon-controlled rectifier (LVT SCR) devices are sometimes used for their reduced trigger voltages. Such devices have been implemented, for example, in sub-micrometer CMOS integrated circuit products, for example, as a grounded-gate n-channel CMOS device. While some low-voltage triggered silicon-controlled rectifiers have relatively lower trigger voltages, they still may still suffer from the risk of latch-up during normal operational conditions of the circuit they are intended to protect.
U.S. Pat. No. 8,455,947 describes a fin field-effect transistor (FinFET) type device which can be used for electrostatic discharge protection. The device comprises a bipolar device portion and an n-channel metal oxide semiconductor device portion, the two portions being connected to one another. Each of the bipolar device portions and n-channel metal oxide semiconductor device portions comprises first, second and third doped regions. Each n-channel metal oxide semiconductor device portion is directly coupled to the bipolar device portion via the second doped portion of the bipolar device portion and the differently doped region of the n-channel metal oxide semiconductor device portion. A gate is formed which is effectively wrapped around the second doped region of the n-channel metal oxide semiconductor device portion. The resulting configuration has the bipolar device portion and the n-channel metal oxide semiconductor device portion that have different orientations, which can be difficult to implement in current state of the art bulk FinFET technology.
US 2009/0309167 describes the use of electrostatic protection devices in a two-stage electronic device in which a first stage and a second stage are respectively connected to an input line and an output line as well to one another, and, to primary and secondary voltage supplies. The ESD protection devices are provided at the input and the output of the electronic device and are connected between input and output lines and each of the primary and secondary supplies. The ESD protection devices can be configured as either a metal oxide semiconductor device or as a fin-based bipolar device where the bipolar device forms a silicon-controlled rectifier device.
However, the disclosed ESD protection devices have an extra doped epitaxial layer to provide electrostatic discharge protection. In addition, such devices are not low voltage and do not address the issue of latch-up and latch-up immunity.
US 2007/0262386 describes an electrostatic discharge protection device in which a plurality of electrostatic discharge (ESD) protection elements are connected in parallel, wherein each ESD protection element includes a fin structure. At least one gate region is formed on or above the fin structures which is connected to a gate control circuit. The gate control circuit acts as a trigger for the electrostatic discharge protection device. The fin structures may be implemented in multi-gate field-effect transistor technology and each fin may comprise a stacked silicon-controlled rectifier (SCR) structure in which a plurality of SCR elements are provided with no isolation structures, for example, shallow trench isolation structures, between the SCR elements.
In this case, the gate control circuits are connected in parallel with an element of an electrical circuit that is to be protected. The detection of an electrostatic discharge event changes the state of the gate to which the gate control circuit is connected so that the current generated by the event can be dissipated. Whilst a SCR structure is provided, the trigger voltage is determined by the gate control circuit and not by the SCR structure itself.
Based on the foregoing references discussed above, there remains a need for low-voltage triggered silicon-controlled rectifiers that have relatively high trigger voltages with increased immunity to latch-up during normal operating conditions. Moreover, none of the foregoing references disclose an implementation of an electrostatic discharge protection device in bulk fin field-effect transistor technology.
In addition, with the trend towards sub-20nm node technology and the associated modifications required in processes to be able to shrink the footprint of bulk fin field-effect transistor type devices, fin widths need to be considered as it has been shown that they are important parameters relating to electrostatic discharge characteristics as discussed by A. Griffoni et al. in “Next generation bulk FinFET devices and their benefits for ESD robustness”, EOS/ESD Symposium, 2009, pages 59 to 68. For example, all current produced due to electrostatic discharge needs to be discharged through the fins, which due to their small sizes, tend to induce localised ‘hot spots’ which results in a deterioration in robustness against electrostatic discharge.